The use of copper for forming the metal interconnect lines in integrated circuits is finding increasing usage due to the superior properties of copper compared to the widely used aluminum lines. One of the primary challenges in integrated circuit fabrication is reducing the RC time delay. An important component of the RC time delay is the resistance and the capacitance present in the metal lines that connect the various devices that comprise the integrated circuit. The resistivity of copper is 1.72×10−6 Ohm-cm versus that of aluminum which is 2.82×10−6 Ohm-cm. This reduced resistivity will reduce the RC delay associated with copper lines. In addition copper has superior resistance to electromigration and higher reliability when compared to commonly used aluminum alloys.
In general integrated circuit metal lines are formed in dielectric layers. These dielectric layers typically comprise silicon oxide or contain silicon oxide. In a typical damascene process for forming an integrated circuit copper line a trench is first formed in a dielectric layer which is formed over a silicon substrate containing electronic devices such as transistors, diodes, etc. This is illustrated in FIG. 1 where the dielectric layer 10 is formed over a silicon substrate. Using standard silicon processing technology a trench 20 is formed in the dielectric layer 10. Because copper reacts with silicon oxide, it is necessary to confine it using a barrier layer. A commonly used barrier layer is tantalum nitride (TaxNy) which is formed on the dielectric layer before the formation of the copper layer. A TaxNybarrier layer 30, 35 is shown in FIG. 1. The TaxNyis formed in a blanket deposition resulting in region 35 which lines the trench and region 30 which forms on the surface on the dielectric layer 10 outside the trench. Following the formation of the TaxNybarrier layer a thick layer of copper is formed. Using standard processing techniques such as chemical mechanical processing (CMP) the excess copper is removed leaving that portion of copper 40 which forms in the trench. To complete the process the portions of the barrier layer which are not cover by copper (i.e. regions 30 in FIG. 1) must be removed. Using existing methods the selective removal of the TaxNy layer is a very difficult process. CMP processes are often used to remove the exposed TaxNy layer 30 but this often results in dishing of the exposed copper surface an erosion of the underlying dielectric layer 10. Wet chemical etching of the exposed TaxNy layer is difficult because most of the chemical solutions which etch TaxNy will attack the underlying dielectric material and etch or damage the exposed copper surfaces. A method is therefore needed to selectively etch TaxNy layers without damaging the underlying dielectric layer and/or the exposed copper surface.